1. Field of the Invention
The present invention relates to semiconductor memory devices and, more specifically, to flash memory devices supporting a successive burst read mode.
This U.S non-provisional patent application claims priority under 35 U.S.C § 119 of Korean Patent Application 2006-14783 filed on Feb. 15, 2006, the entirety of which is hereby incorporated by reference.
2. Discussion of Related Art
Flash memory is a type of nonvolatile rewritable memory useful in a wide variety of data applications that require occasional writing and/or rewriting of data, nonvolatile storage, and relatively high-speed read capability. To increase the read speed, some flash memory devices include a “burst-read” or “page-read” operation. A flash memory device with this capability responds to a read request by reading a “page” of memory.
Flash memory devices may be classified into NAND-type flash memory devices (hereinafter referred to as “NAND flash memory devices”) and NOR-type flash memory devices (hereinafter referred to as “NOR flash memory devices”). A cell array of a NOR flash memory device is configured as a plurality of memory cells connected in parallel to one bitline, while a NAND flash memory device is configured in which a plurality of memory cells are connected in series to one bitline. Since NOR flash memory devices have much higher operation speed than NAND flash memory devices, they are being used in a variety of applications requiring high-speed characteristic.
A read operation is conducted similarly to a random access operation. An external system inputs a specific address, on a memory cell array, where data to be read is positioned and inputs a read command. Thereafter, if an output enable signal is activated, it is synchronized with a clock signal from the system to output data corresponding to the input address. However NOR flash memory devices support a burst read mode, which is suitable for supporting a high-speed read operation. In the burst read mode, data larger than an input/output unit (I/O configuration: for example, ×16 structure) are output as many as the number of clocks corresponding to a burst length (hereinafter referred to as “BL”) by once input of an address and a command in synchronization with a clock signal. Particularly in the burst read mode, all memory cells connected to a specific wordline may be sensed and output sequentially after being selected. Alternatively, in the case where a plurality of wordlines is selected, data of all cells connected to the wordlines may be successively output to the exterior after being sensed sequentially. For such a burst read operation, a memory device receives a start address of a cell array. Thereafter, burst addresses are internally generated using a count-up method to be successively supplied to a read circuit. Accordingly, the system has only to supply addresses once in the burst read mode.
Sense amplifier groups corresponding to the number of words (1 word=16 bits) to be output per sector are needed to support a burst read mode. Due to an operation characteristic of a column gate circuit selecting the sense amplifier groups and bitlines of a cell array, a start address group of the burst read mode is addressed. In case of a memory including a sense amplifier corresponding to four words per sector, a start address group may be categorized as four kinds such as, for example, 4N, 4N+1, 4N+2, and 4N+3. The start address group includes information on the number of valid words among initially output 4-word data. In a burst read mode where cell data should be sensed and output successively, if a start address is positioned at the final stage of a selected wordline, time is required for selecting and accessing a new wordline. Thus, the initially output 4-word data includes not only valid data corresponding to an assigned address but also invalid data for outputting data that are continuous for an extra time when access is conducted to the next wordline. A word boundary means a period corresponding to invalid data among four words output initially. A memory device informs a system that a word boundary is invalid data included in initially output 4-word data, through a ready pin (RDY pin). Generally, an output of a ready pin (RDY pin) is a ready signal RDY where a burst read mode starts. The ready signal RDY transitions to a low level during an initial read period. The ready signal RDY is output high during a period where effective data is output at words (e.g., four words) corresponding to an initial burst length but transitions to a low level when data corresponding to the word boundary is output, informing the system that the data is invalid data. The ready signal RDY transitions to a high level from outputting data of a second burst length BL and are maintained at the high level until the burst read operation is ended.
FIG. 1 is a timing diagram illustrating levels of a ready signal RDY and a wordline boundary generated at a burst read operation of the conventional memory device. Specifically, FIG. 1 shows a ready signal RDY indicating a word boundary existing in four words that are initially output when a burst start address A0 is given as a start address group.
If an address valid signal nAVD is synchronized with a rising edge of a clock signal CLK while being in a low level, a memory device enters a burst read mode. An input address A0 is synchronized with an external clock to successively conduct the burst read operation. Data are continuously output during an initial read period where access is performed for a cell corresponding to burst start address A0. The initial read period means a period from a low level of a valid signal nAVD and a rising edge of a clock signal associated with the output time of the initial data. Therefore during the initial read period, a ready signal RDY is maintained for a time T1 to inform the system that the data is invalid. After the initial read period, data are continuously sensed and output to conduct the burst read operation. However, 4-word data (under the premise that BL=4), has only three valid words because the start address group is 4N+1. Among the initial four words that are successively output, the three valid words are 1—2, 1—3, and 1—4. Output word 1—4 is dummy data among the words output by means of the initial read operation. Accordingly the memory device enables the ready signal RDY to transition to a low level during a clock cycle T2 where the last word output among the initially output words informs, the system that the data is invalid.
As described above, during one burst read mode, there are two low level periods of the ready signal RDY for informing the system that data are invalid data of the initial read period T1 and a word boundary period T2. Since the system must check a word boundary through the ready signal RDY each time entering a burst read mode, it must sense a second low period T2 of the ready signal RDY. The system must sense a length and a position of the second low level T2 of the ready signal RDY to receive output burst data without error. In the burst read mode, the system must sense a low level of the ready signal RDY twice. Thus, the system may encounter the damage of hardware or software for setting an interrupt which results from twice ready signal RDY.